システム - タイマー

ARM7側、ARM9側それぞれ4つずつ、合計8個のタイマーがある。

マスタークロックは 33.4 MHz で、

and an enabled counter normally goes up by one on each beat of this clock. There is a piece of hardware called a prescaler associated with each timer, which allows it to count up every 64, 256, or 1024 clocks instead of after every one. Timers can also be cascaded together, so that one will count up when the timer below it overflows, instead of being based directly on the clock.

The timers are 16 bit unsigned numbers, i.e. they can count up to 65536, after which they will overflow. When a timer overflows, it reloads the counter with a latched value and will trigger an interrupt if you have requested it.

The latch is set whenever you write to the timer data register, and cannot be read. This latched value is only loaded into a timer when it is re-enabled, or when it overflows (a write just sets the latch, and does not directly affect the counter).

To make a timer overflow at a particular frequency, you set the latch accordingly. A timer with a latched value of 0 counting at 33.4 MHz / 1024 will overflow every 65536*1024 clocks, or about once every two seconds. To make the same timer overflow with a period of X seconds, the calculation looks like:

latch = 65536 - X*33400000/1024

For an arbitrary timer, change the 1024 depending on the prescaler.
Register Details
Location Register Type 15..8 7 6 5..3 2 1..0
0x04000102:16 TIMER_CR(0) R/W 0 Enable IRQ 00 Prescaler
0x04000106:16 TIMER_CR(1) R/W 0 Enable IRQ 0 Cascade Prescaler
0x0400010A:16 TIMER_CR(2) R/W 0 Enable IRQ 0 Cascade Prescaler
0x0400010E:16 TIMER_CR(3) R/W 0 Enable IRQ 0 Cascade Prescaler

   * Prescaler setting (controls counting frequency) (bits 0-1)
         o 00: Every clock
         o 01: Every 64 clocks
         o 10: Every 256 clocks
         o 11: Every 1024 clocks 
   * Cascade (bit 2):
         o When set, the timer is part of a cascade chain timer, in which the lower timer's overflow is the update frequency, and the frequency bits are ignored. This bit is ignored for timer 0, since it does not have a lower timer to cascade from. 
   * IRQ (bit 6)
         o When set, an interrupt request is generated each time the timer overflows. 
   * Enabled (bit 7)
         o When set, the timer proceeds as normal, otherwise the timer is halted. 

Location Register Type Description
0x04000100:16 TIMER_DATA(0) R Get count
0x04000100:16 TIMER_DATA(0) W Set latch
0x04000104:16 TIMER_DATA(1) R Get count
0x04000104:16 TIMER_DATA(1) W Set latch
0x04000108:16 TIMER_DATA(2) R Get count
0x04000108:16 TIMER_DATA(2) W Set latch
0x0400010A:16 TIMER_DATA(3) R Get count
0x0400010A:16 TIMER_DATA(3) W Set latch

Note:

   * Latch writes do not take effect immediately. The latch is only transferred into the counter on an overflow, or when the enable bit in the corresponding control register is set.
   * Timers (and almost all other hardware) runs off of a 33.4 MHz clock [[@wikiへ>http://kam.jp"><META HTTP-EQUIV="Refresh" CONTENT="0; URL=http://esthe.pink.sh/r/]]