1 Vdd (3.3V)
PHI is a programmable clock output (disabled by default, the selectable frequencies vary between the DS and GBA, see WAIT_CR)
During 'compatible' mode transfers (/CS2), AD0..AD15 are instead A0..A15, and A16..A23 serve as D0..D7.
Multiplexed bus accesses can be either sequential or non-sequential.
* Non-sequential reads are done by asserting the low 16 bits of the desired address on AD0..AD15, and taking /CS low, which will latch the counter. The actual data fetch is the same as a sequential read.
* Sequential reads are done by strobing /RD low: data will be output on AD0..AD15 and should be valid on the rising edge of /RD.
A16..A23 must be valid at all times, since the latchable up-counter is only 16 bits wide. The counter is clocked on each rising edge of /RD.