ハードウェア - カードレジスタ

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「ハードウェア - カードレジスタ」(2007/06/18 (月) 09:32:56) の最新版変更点

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**CARD_SPI_CR (0x040001A0:16)
bit	mode	name	description
15	W	Enable	Enables the SPI unit (reads as 0?)
14	R/W	IRQ	Fire an IRQ when transfer is done
13	R/W	/Last_Trasmission	0: Last write, 1: Part of a sequence
12..8	W?	?	?
7	R	Busy	0: Idle, 1: Transfer in progress
6	R/W	Mode	1: Talk to SPI device on DS Card
5..2	R	-	000
1..0	R/W	SPI frequency	0: 4.19MHz, 1: 2.10MHz, 2: 1.05MHz, 3: 524kHz

By comparison with the ARM7, some of the writable bits may select bus speed or 8/16 bit mode. Fixme: test this (write-and-stick bits = 00ffe043). 

**CARD_SPI_DATA (0x040001A2:16)
bit	mode	name	description
15..8	W?	?	?
7..0	R/W	SPI data	*

* A read returns the last value transferred in, while a write starts a transfer cycle.

For more information, see the SPI page for more information on SPI bus transfers, and Chips for information on some of the save memories used on DS cards. 

**CARD_CR2 (0x040001A4:32)
bit	name	description
31	R/W	enable/start	 
30	R/W	is command	is this a send command or a read?
29	R/W	reset	controls the status of the reset line?
28	R/W	?	set after setting the encrypt registers
27	R/W	?	 
26..24	R/W	datablock count	used for reading multiple of 512 bytes. 7=invalid
23	R	data ready	err, in one place it reads from one reg, and in the other, another
22	R/W	?	 
21..16	R/W	length of some sort	 
15	W	?	set after setting encrypt registers, elsewhere
14	R/W	encrypt	1=encrypt this command, 0=nah, send it plaintext
13	R/W	?	only used on the binary transfers (10,20,A0,40,60)
12..0	R/W	Data transfer size	(does not count size of command itself)

ff7f7fff 

**Write-onlys (0x040001B0..1BB)

Write-only These are encrypt registers, they control the internal encryptor/decryptor, versus the 3C command which tells the card to set its encryptor/decryptor.

    * 0x040001B0:32 = CARD_1B0 (32 bits)
    * 0x040001B4:32 = CARD_1B4 (7 bits)
    * 0x040001B8:16 = CARD_1B8 (32 bits)
    * 0x040001BA:16 = CARD_1BA (7 bits) 

Command registers

    * 0x040001A8:8
    * 0x040001A9:8
    * 0x040001AA:8
    * 0x040001AB:8
    * 0x040001AC:8
    * 0x040001AD:8
    * 0x040001AE:8
    * 0x040001AF:8 

Both sets of write-only registers read as 00's. 

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