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ARM9
WAIT_CR (0x04000204:16) Bits Description
15 Main RAM bus priority (0: ARM9, 1: ARM7)
14..12 110
11 DS Card Owner (0: ARM9, 1: ARM7)
10..8 000
7 GBA Cart Owner (ROM and SRAM) (0: ARM9, 1: ARM7)
6 ?
5 ?
4 ?
3..2 GBA ROM wait state control
1..0 GBA SRAM wait state control
This register is settable to 0xE8FF, clearable to 0x6000.
Tested wait states a bit, although I didn't work out the absolute numbers, I timed relative read speed for several areas of memory, varying the low 4 bits of WAIT_CR.
Taking ITCM as a base case of 0 Area tested Additional wait states
Setting 0 13
Setting 1 11
Setting 2 9
Setting 3 21
Main RAM 8
'Shared' RAM 4
ITCM 0
Notes:
* Setting X indicates the speed of GBA ROM or SRAM when X is used in the bits in WAIT_CR. The ROM reads were non-sequential, haven't thought of a good test for seq. reads.
* I'll test out PHI in a little bit, need to destroy another GBA cart or take apart a DS to tap the PHI line.
* SRAM reads were done at 8 bits, ITCM reads at 32 bits, and all others at 16 bits.
The Owner bits control which CPU can access the GBA cart and DS cards. The GBA cart bit controls both the compatibility bus at 0x0A00xxxx and the address-data multiplexed bus at 0x08000000..0x09FFFFFF, and the DS card bit controls the card-related registers and machinery.
ARM9 bios does WAIT_CR = 0x2000, some main RAM writes/reads, then WAIT_CR = 0x6000, then a lot of init code, then WAIT_CR = 0xE880
ARM7
WAIT_CR 0x04000204:16
15..0 ?
sets to e8ff, clears to e880 (only sometimes)
Setting ARM9 to 0000 results in arm9=6000, arm7=607f Setting ARM9 to FFFF (from 6000) results in arm9=e8ff, arm7=e880 setting arm7 to 0000, arm9=6000, arm7=6000 setting arm7 to ffff, arm9=6000, arm7=607f
ARM9
WAIT_CR (0x04000204:16) Bits Description
15 Main RAM bus priority (0: ARM9, 1: ARM7)
14..12 110
11 DS Card Owner (0: ARM9, 1: ARM7)
10..8 000
7 GBA Cart Owner (ROM and SRAM) (0: ARM9, 1: ARM7)
6 ?
5 ?
4 ?
3..2 GBA ROM wait state control
1..0 GBA SRAM wait state control
This register is settable to 0xE8FF, clearable to 0x6000.
Tested wait states a bit, although I didn't work out the absolute numbers, I timed relative read speed for several areas of memory, varying the low 4 bits of WAIT_CR.
Taking ITCM as a base case of 0 Area tested Additional wait states
Setting 0 13
Setting 1 11
Setting 2 9
Setting 3 21
Main RAM 8
'Shared' RAM 4
ITCM 0
Notes:
* Setting X indicates the speed of GBA ROM or SRAM when X is used in the bits in WAIT_CR. The ROM reads were non-sequential, haven't thought of a good test for seq. reads.
* I'll test out PHI in a little bit, need to destroy another GBA cart or take apart a DS to tap the PHI line.
* SRAM reads were done at 8 bits, ITCM reads at 32 bits, and all others at 16 bits.
The Owner bits control which CPU can access the GBA cart and DS cards. The GBA cart bit controls both the compatibility bus at 0x0A00xxxx and the address-data multiplexed bus at 0x08000000..0x09FFFFFF, and the DS card bit controls the card-related registers and machinery.
ARM9 bios does WAIT_CR = 0x2000, some main RAM writes/reads, then WAIT_CR = 0x6000, then a lot of init code, then WAIT_CR = 0xE880
ARM7
WAIT_CR 0x04000204:16
15..0 ?
sets to e8ff, clears to e880 (only sometimes)
Setting ARM9 to 0000 results in arm9=6000, arm7=607f Setting ARM9 to FFFF (from 6000) results in arm9=e8ff, arm7=e880 setting arm7 to 0000, arm9=6000, arm7=6000 setting arm7 to ffff, arm9=6000, arm7=607f
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